Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
In Motion Estimation (“ME”) for processing image frames, it is well-known to use an ME algorithm. Many of such ME algorithms depend upon a Sum of Absolute Differences (“SAD”) calculation for providing a cost metric for making ME decisions. With respect to a current image frame (“C”) being processed as related to a previous or reference image frame (“P”), a sum of absolute differences calculation may be performed on each associated pair of pixels in the frames. Thus, for an image frame having a width “Width,” namely Width columns of pixels, and a height “Height”, namely Height rows of pixels, a sum of absolute differences calculation for processing C and P image frames may be mathematically expressed as:
      S    ⁢                  ⁢    A    ⁢                  ⁢    D    =            ∑              x        =        1            Width        ⁢                  ⁢                  ∑                  y          =          1                Height            ⁢                          ⁢                                            C                          x              ,              y                                -                      P                          x              ,              y                                                  
More generally, an absolute value (“ABS”) of A minus B, namely |A−B|, may have a positive difference or a negative difference, even though the magnitude of either of such differences is always positive. Mathematically, a positive difference may be expressed as A−B, and a negative difference may be expressed as B−A, or stated another way:
                A      -      B            =      {                                                      A              -              B                                                          A              ⁢                              >                _                            ⁢              B                                                                          B              -              A                                                          A              <              B                                          =              {                                            (                              A                +                                  B                  _                                            )                                      (                              A                +                                  B                  _                                            )                                +                      1            ⁢                                                                                A                    ⁢                                          >                      _                                        ⁢                    B                                                                                                                    A                    <                    B                                                                                          
For an image frame of a reasonable viewing size, there are many pixels to process. Furthermore, each pixel may be expressed using multiple bits. Thus, there is a significant amount of processing to be done for a sum of absolute differences calculation on image frames. Furthermore, the processing time is conventionally increased by waiting for forward propagation of each carry bit.
Accordingly, it would be desirable and useful to provide a sum of absolute differences calculation in circuitry with faster processing.